NOT gate using CMOS technology. Figure created using Digi-Key Scheme-it (digikey.com/schemeit/)
NMOS circuits have an inherent flaw - although they use transistors efficiently, they are left wide-open and waste power whenever their output goes low and current flows to ground. The normal method to avoid wasting power this way is to implement the inverse function where the NMOS current-limiting resistor normally goes. That way, current will be completely interrupted when the pull-down network would pass it through to ground, while maintaining that the output pin will only go high when it is meant to. CMOS (complementary MOS) technology is the most common implementation of this solution.
To the left is the NOT gate shown earlier, now with a second transistor blocking excessive power loss. The second transistor, which implements the needed inverse function, is a PMOS transistor. PMOS transistors have a natural closed state opposite that of NMOS transistors. They are distinguished from NMOS transistor symbols by a small circle at the junction of the input and the bridge (in this website, an upward arrow is used instead). Because of their opposite natural state, the group of PMOS transistors forms a "pull-up network". By using PMOS transistors for the pull-up network, all that is left to construct the inverse function from the original pull-down network is to make the following two changes:
To the left is the NOT gate shown earlier, now with a second transistor blocking excessive power loss. The second transistor, which implements the needed inverse function, is a PMOS transistor. PMOS transistors have a natural closed state opposite that of NMOS transistors. They are distinguished from NMOS transistor symbols by a small circle at the junction of the input and the bridge (in this website, an upward arrow is used instead). Because of their opposite natural state, the group of PMOS transistors forms a "pull-up network". By using PMOS transistors for the pull-up network, all that is left to construct the inverse function from the original pull-down network is to make the following two changes:
- Place in parallel every transistor that used to be in series
- Place in series every transistor that used to be in parallel
Boolean function implemented with CMOS technology. Click to view larger figure. Figure created using Digi-Key Scheme-it (http://www.digikey.com/schemeit/)